EE295 - ASIC Design Using VHDL

Test Survey

Assignment:

• "Level-Sensitive Scan Design (LSSD) Provides Benefits for Testability and Product Development", By David E. Lackey, Integrated Systems Future Issue
• "An ASIC Foundry View of Design And Test", By S Oakland, J Monzel, R Bassett, P Gillis Presented at the 1994 Int'l Test Conference

Outline:

• Scan-Based Test
• Boundary Scan
• BIST

Resources

• Text Books:
  • "The Test Access Port and Boundary-Scan Architecture" Colin M. Maunder and Rodham E. Tulloss (Eds), IEEE Computer Society Press, 1990
• Vendors:
  • Texas Instruments IEEE 1149.1/JTAG/Boundary Scan
  • TI's 'What is IEEE 1149.1?' Application Note
  • TI's Suggested Design Flow Application Note
  • Synopsys' Design For Test ( DFT ) Products Data Sheet
  • Synopsys' DFT Products
  • Synopsys Application Note "How to Avoid Test Surprises when Using Test Compiler", JHLD-099405 1994
  • IBM ASIC - Level Sensitive Scan Design Application Note
  • LSSD in CMOS 5L Application Note