Sequential Logic Synthesis (part I)

Index

o Design unit overview
o The RTL style
o Concurrent vs. Sequential statements
o Variables vs. Signals
o Register inference
o Edge expressions


Design Unit overview

o Packages
o Declarations
o Components
o Constants
o (Sub)types
o Subprograms (functions and procedures)
o Entities
o Architectures
o Declarations
o Local signals
o Concurrent statements
o (Conditional) signal assignments - delays ignored
x <= a + b when c1 else a + c;
o Subprogram calls
o Components instantiations
o Generate statements
o (Nested) blocks
o Processes
o Configurations (default: entity to MRA architecture)


Process

The elementary unit of behavior - described by a discrete algorithm

o Declarations
o Local variables
o Sequential statements
o Signal assignments
o Subprogram calls
o Variable assignments
x := a + c;
o Control flow stmts
o Conditional stmts
o Priority (if ..)
o Case
o Loops
o Computable (for ..)
o Non-computable (while .. loop)
o next, exit
o null
o wait
All sequential statements except from wait can be used in subprograms as well.



Concurrent vs. Sequential statements

o Concurrent stmts:
o Model asynchronous dataflow
o Order is irrelevant, i.e. parallel assignments
o Only signals allowed
o If more than one drivers for a signal, it must be of a resolved type
o Are translated to processes:
o x<= a;
o process (a)
begin
x<a;
end process;
o process
begin
x<= a;
wait on a;
end process;
o Sequential stmts:
o Order matters!
o Model discrete algorithms
o Signals AND variables are allowed


Variables vs. Signals

o Variables:
o only used inside processes and subprograms
o assignment is immediate
o used to store temporary results or current signal values
o Signals:
o correspond to (memory-less) nets
o the only form of communication between processes and other concurrent stmts
o inside a process only the last signal assignment is effective


Inferring Synchronous Logic

o Why avoid explicit register instantiation
o (+ve) <edge> (clk is one bit encodable):
o clk'event and clk='1'
o not clk'stable and clk='1'
o Two forms (<edge> cannot be used as on operand):
o wait until <edge>;
o if <edge> ....
o Do not assign to/from clock signals!
o If more than one clocks, use different processes for each
o Signals stored in FFs:
o Signals driven by the process
o Variables that are read before they are set
o Implicit/explicit state vectors
o Example: modulo-10 counter



Too many registers!

o Signals driven by a process containing <edge> expressions are registered

o To avoid extra registers separate combinational from sequential processes
example

o In general, each process and concurrent signal assignment produce a piece of HW
o Use a single process for each type of logic


Alternative forms of FF inference

o Basic DFF:
process(clk,data)
begin
if (clk'event and clk='1') then
q<=data;
end if;
end process;
o DFF with asynchronous reset:
prosess(clk,reset_low,sync_data)
begin
if reset_low='0' then
q<='0';
elsif (clk'event and clk='1') then
q<=sync_data;
end if;
end process;
o DFF with synchronous reset:
process(reset_low,clk,sync_data)
begin
if (clk'event and clk='1') then
if reset_low='0' then
q<='0';
else q<=sync_data;
end if;
end if;
end process;
o In general, if <edge> more flexible than wait <edge> but more dangerous:
o Do NOT use more than one if <edge> expressions in a process - but you can use many wait <edge>
o Do NOT assign a value to a variable/signal on a FALSE branch of an if <edge> expression
o Watch out! if stmts can infer:
o Muxes
o Latches
o FFs
o Combinational logic in for loops and subprograms


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Last Modified: December 21/1995