--
-- Rcsid[] = "$Id: g4bctr.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--

-- 4-bit up-down counter

entity g4bctr is
port(QD,QC,QB,QA,carry: out bit;
     dataD,dataC,dataB,dataA,clk,UD,load,enP,enT,VCC: in bit);
end;

architecture structure of g4bctr is

signal n2, n3, n4, n5, n6, n7, n8, n9: bit;
signal n10, n11, n12, n13, n14, n15, n16, n17, n18, n19: bit;
signal n20, n21, n22, n23, n24, n25, n26, n27, n29: bit;
signal n30, n31, n32, n33, n34, n35, n36, n37, n38, n39: bit;
signal n40, n41, n42, n43, n44: bit;
signal QAbar, QBbar, QCbar, QDbar: bit;
signal QA_buf, QB_buf, QC_buf, QD_buf: bit;

begin
U2 : inv_gate generic map(1,1) port map(n2,UD);
U3 : inv_gate generic map(1,1) port map(n3,load);
U4 : inv_gate generic map(1,1) port map(n4,enP);
U5 : inv_gate generic map(1,1) port map(n5,enT);
U6 : and_gate generic map(1,1) port map(n6,n3,dataA);
U7 : and_gate generic map(1,1) port map(n7,n3,dataB);
U8 : and_gate generic map(1,1) port map(n8,n3,dataC);
U9 : and_gate generic map(1,1) port map(n9,n3,dataD);
U10 : inv_gate generic map(1,1) port map(n10,n3);
U11 : and_gate generic map(1,1) port map(n11,n4,load);
U12 : and_gate generic map(1,1) port map(n12,n2,QA_buf);
U13 : inv_gate generic map(1,1) port map(n13,n2);
U14 : and_gate generic map(1,1) port map(n14,n13,QAbar);
U15 : nor_gate generic map(1,1) port map(n15,n12,n14);
U16 : and_gate generic map(1,1) port map(n16,n2,QB_buf);
U17 : inv_gate generic map(1,1) port map(n17,n2);
U18 : and_gate generic map(1,1) port map(n18,n17,QBbar);
U19 : nor_gate generic map(1,1) port map(n19,n16,n18);
U20 : and_gate generic map(1,1) port map(n20,n2,QC_buf);
U21 : inv_gate generic map(1,1) port map(n21,n2);
U22 : and_gate generic map(1,1) port map(n22,n21,QCbar);
U23 : nor_gate generic map(1,1) port map(n23,n20,n22);
U24 : and_gate generic map(1,1) port map(n24,n2,QD_buf);
U25 : inv_gate generic map(1,1) port map(n25,n2);
U26 : and_gate generic map(1,1) port map(n26,n25,QDbar);
U27 : nor_gate generic map(1,1) port map(n27,n24,n26);
U28 : nand_gate generic map(1,1) port map(carry,n5,n15,n19,n23,n27);
U29 : inv_gate generic map(1,1) port map(n29,n11);
U30 : nand_gate generic map(1,1) port map(n30,n15,n11);
U31 : nand_gate generic map(1,1) port map(n31,n15,n11,n19);
U32 : nand_gate generic map(1,1) port map(n32,n15,n11,n19,n23);
U33 : and_gate generic map(1,1) port map(n33,QA_buf,n29,n10);
U34 : and_gate generic map(1,1) port map(n34,QAbar,n11);
U35 : and_gate generic map(1,1) port map(n35,QB_buf,n30,n10);
U36 : and_gate generic map(1,1) port map(n36,QBbar,n11,n15);
U37 : and_gate generic map(1,1) port map(n37,QC_buf,n31,n10);
U38 : and_gate generic map(1,1) port map(n38,QCbar,n11,n15,n19);
U39 : and_gate generic map(1,1) port map(n39,QD_buf,n32,n10);
U40 : and_gate generic map(1,1) port map(n40,QDbar,n11,n15,n19,n23);
U41 : or_gate generic map(1,1) port map(n41,n33,n34,n6);
U42 : or_gate generic map(1,1) port map(n42,n35,n36,n7);
U43 : or_gate generic map(1,1) port map(n43,n37,n38,n8);
U44 : or_gate generic map(1,1) port map(n44,n39,n40,n9);
U45 : DFF1  port map(QA_buf,n41,clk,VCC,VCC);
U45b : buf_gate port map (QA,QA_buf);
u45a : inv_gate port map(QAbar, QA_buf);
U46 : DFF1  port map(QB_buf,n42,clk,VCC,VCC);
U46b : buf_gate port map (QB,QB_buf);
u46a : inv_gate port map(QBbar, QB_buf);
U47 : DFF1  port map(QC_buf,n43,clk,VCC,VCC);
U47b : buf_gate port map (QC,QC_buf);
u47a : inv_gate port map(QCbar, QC_buf);
U48 : DFF1  port map(QD_buf,n44,clk,VCC,VCC);
U48b : buf_gate port map (QD,QD_buf);
u48a : inv_gate port map(QDbar, QD_buf);
end structure;

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