See Also

A design should not contain an input clock pin that fans out to more than one gated clock (that is, an AND or OR gate that is synchronized with a register and used as a clock signal). To effectively save power using a gated clock, you should make sure all the input clock pins in a design each fan out to only one gated clock. The following image shows an example of an input clock pin that fans out to more than one gated clock:

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