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To use the Model Technology^™ ModelSim^®-Altera^® (OEM) software to perform a functional simulation of a VHDL or Verilog HDL design that contains Altera-specific components using command-line commands: Read This First

1. If you have not already done so, perform 2. Set Up a Project with the ModelSim-Altera Software (Command-Line).

2. If your design contains the altgxb megafunction, to map to the precompiled Stratix^™ GX functional simulation model libraries type the following command at the ModelSim prompt:

   vmap altgxb \quartus\eda\sim_lib\modelsim\<verilog or vhdl>\altgxb\ 
   

   If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

3. To map the VHDL 93-compliant design libraries, type the following commands at the ModelSim prompt:

   vmap lpm \<ModelSim-Altera install directory>\altera\<verilog or vhdl>\lpm\ 
vmap altera_mf \<ModelSim-Altera install directory>\altera\<verilog or vhdl>\altera_mf\ 

   If you want to use VHDL 87-compliant simulation libraries, you must map lmf and altera_mf to the \<ModelSim-Altera install directory>\altera\220model_87\ and \<ModelSim-Altera install directory>\altera\altera_mf_87\ directories, respectively.

4. To compile the Verilog or VHDL Design Files and test bench files (if you are using a test bench), type the following commands at the ModelSim prompt:

   For VHDL designs:

   vcom -work work <design name>.vhd 
vcom -work work <test bench>.vhd 

   For Verilog HDL designs:

   vlog -work work <design name>.v 
vlog -work work <test bench>.v 

5. To load the design:

   For VHDL designs:

   vsim work.<top-level design entity> 

   For Verilog designs:

   vsim -L \<ModelSim-Altera install directory>\altera\verilog\lpm\ -L \<ModelSim-Altera install directory>\altera\verilog\altera_mf\ work.<top-level design entity> 

6. Perform the functional simulation in the ModelSim-Altera software.

If you are simulating an ARM®-based Excalibur™ design, the bus functional model generates the output.dat bus functional model simulation file. Refer to ModelSim software documentation for more information on how to view and interpret the results of the simulation.

7. To continue with the ModelSim-Altera simulation flow and perform a timing simulation, return to one of the following steps:

   • 2. Set Up a Project with the ModelSim-Altera Software
   • 2. Set Up a Project with the ModelSim-Altera Software (Command-Line)

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