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To use the Cadence NC-Verilog software to perform a prerouting functional simulation of a Verilog HDL design that contains Altera-specific components using command-line commands:

1. If you have not already done so, perform 1. Set Up the NC-Verilog Working Environment.

2. Create a work library in the project directory by typing the following command at the command prompt:  More Details

mkdir <work library> 

3. Copy the cds.lib and hdl.var files, which are located in the \<NC-Verilog installation directory path>\tools\inca\files\ directory, to the \<project directory>\simulation\ncsim directory.

4. Edit the cds.lib and hdl.var files as follows:

   File Name	File Contents	Function
   cds.lib	DEFINE <work library> ./work	Maps the <work library> to the physical location of the work library.
   hdl.var	DEFINE WORK <work library>	Maps the NC-Verilog variable WORK to the <work library>.

5. If your design contains the altgxb megafunction, add the following lines to the cds.lib file to map to the precompiled Stratix^™ GX functional simulation model libraries:

DEFINE altgxb \quartus\eda\sim_lib\ncsim\verilog\altgxb

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

6. If your design contains CAM, RAM, or ROM functions, and you are using a Hexadecimal (Intel-Format) File (.hex), to convert the memory initialization data without using the convert_hex2ver utility:

   1. Export the HEX File as a RAM Initialization File (.rif) in the Quartus^® II software.

   2. Add the text parameter lpm_file = "<RIF name>.rif"; for the CAM, RAM, or ROM function to your top-level design or test bench file.

7. If your design contains CAM, RAM, or ROM functions, and you are using a HEX File, to build the convert_hex2ver utility, load the HEX File and initialize the memory:

   1. Build the convert_hex2ver utility.

   2. Type the following command at the command prompt:

   ncelab -loadpli1 <convert_hex2ver utility name>: <work library>.<design name> 

8. To compile the appropriate project files and libraries into the work library, type the following commands at the command prompt from within the project directory:

ncvlog <test bench file> 
ncvlog <design name>.v 
ncvlog \quartus\eda\sim_lib\220model.v 
ncvlog \quartus\eda\sim_lib\altera_mf.v 


If you are using a RIF to specify memory initialization data, add the string -define NO_PLI before 220model.v and altera_mf.v in the above commands.

9. To elaborate and simulate the design, type the following command at the command prompt:

ncelab <work library>.<top-level entity name> 

ncsim <work library>.<top-level entity name> 

10. To continue with the NC-Verilog simulation flow, proceed to one of the following steps:

    • 3. Perform a Timing Simulation with the NC-Verilog Software
    • 3. Perform a Timing Simulation with the NC-Verilog Software (Command-Line)

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