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To use the Cadence NC-VHDL software command line to perform a prerouting functional simulation of a VHDL design that contains Altera-specific components:

1. If you have not already done so, perform 1. Set Up the NC-VHDL Working Environment.

2. Create a work library in the project directory by typing the following command at the command prompt: More Details

mkdir <work library> 

3. Copy the cds.lib and hdl.var files, which are located in the \<NC-VHDL installation directory path>\tools\inca\files\ directory, to the \<project directory>\simulation\ncsim directory.

4. Edit the cds.lib and hdl.var files as follows:

   File Name	File Contents	Function
   cds.lib	DEFINE <work library> ./work DEFINE LPM <work library> DEFINE ALTERA_MF <work library>	Maps the <work library> to the physical location of the work library, and the variables LPM and ALTERA_MF to the work library.
   hdl.var	DEFINE WORK <work library>	Maps the NC-VHDL variable WORK to the <work library>.

When defining library names, do not use library names that begin with numeric characters, for example, 220model.

5. If your design contains the altgxb megafunction, add the following lines to the cds.lib file to map to the precompiled Stratix^™ GX functional simulation model libraries:

DEFINE altgxb \quartus\eda\sim_lib\ncsim\vhdl\altgxb

If your design contains the altgxb megafunction, you must set the value of the pll_areset signal to start high in the test bench or waveform file for the design. If the megafunction does not instantiate a GXB transmitter PLL, you must set the values of the rxanalogreset and rxdigitalreset signals to start high.

6. To compile the appropriate project files and libraries into the work library, type the following commands at the command prompt from within the project directory:

ncvhdl <test bench file> 
ncvhdl <design name>.vhd  
ncvhdl -v93 -work lpm <drive>:\quartus\eda\sim_lib\220model.v 
ncvhdl -v93 -work altera_mf <drive>:\quartus\eda\sim_lib\altera_mf.v 


For the functional simulation libraries for VHDL 87-compliant designs, type the following commands to compile the simulation libraries: ncvhdl [-v87] -work lpm <drive>:\quartus\eda\sim_lib\220model_87.v  ncvhdl [-v87] -work altera_mf <drive>:\quartus\eda\sim_lib\altera_mf_87.v

7. To elaborate the design, type the following command at the command prompt:

ncelab <work library>.<top-level entity name> 

8. To simulate the design, type the following command at the command prompt:

ncsim <work library>.<top-level entity name> 

9. To continue with the NC-VHDL simulation flow, proceed to one of the following steps:

   • 3. Perform a Timing Simulation with the NC-VHDL Software
   • 3. Perform a Timing Simulation with the NC-VHDL Software (Command-Line)

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