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To perform a timing simulation of a Quartus^® II–generated VHDL Output File (.vo) and the corresponding Standard Delay Format Output File (.sdo) with the Synopsys^® VSS software:

1. If you have not already done so, perform 1. Set Up the VSS Working Environment.

2. To generate the VHDL Output File (.vho):

   1. Specify EDA tool settings in the Quartus II software.

   2. Compile the design with the Quartus II software.

   The Quartus II Compiler generates the VHDL Output File and the SDF Output File and places them in the /<project directory>/simulation/vss directory. More Details

3. Add the following lines to your .synopsys_vss.setup file to include the mapping information for the work library, and to direct the VSS software to use the timing simulation libraries during simulation:

   WORK > <work library>
   <device family> > <work library>
   <work library> > <physical path to work library>

4. Create a work library in the project directory by typing the following command at a command prompt: More Details

mkdir <work library> 

5. To compile the VHDL Output File, test bench file (if you are using one) and Altera^® prerouting simulation libraries, type the following commands at a command prompt:

vhdlan /usr/quartus/eda/sim_lib/<device family>_atoms.vhd 
vhdlan /usr/quartus/eda/sim_lib/<device family>_components.vhd 
vhdlan <test bench file> 
vhdlan <design name>.vho 


For VHDL 87-compliant designs for APEX™ 20KE devices, type the following command to compile the VHDL-87 compliant simulation model library instead: vhdlan -vhdl87 /usr/quartus/eda/sim_lib/apex20ke_atoms_87.vhd

6. To back-annotate timing information through the SDF Output File, type the following command at the command prompt (where <VHDL configuration name> represents the configuration name in the test bench file):

   scsim -sdf_top <test bench file> -sdf <design name>.sdo <VHDL configuration name> 

   The VSS software requires each architecture or entity pair in a VHDL Output File or test bench file to have a configuration. The Configuration Declaration is necessary for simulation, but not for synthesis.

7. If your design contains device power up signals, initialize the device power up signal by typing the following commands at the command prompt:

   assign '0' /<test bench entity>/<design entity>/<device power up> 
   run <time> 
   assign '1' /<test bench entity>/<design entity>/<device power up> 

   The variable <device power up> is the name of the device power up signal and <time> is a time value for the minimum time required for the device to initialize.

8. To simulate the design, type the following command at a command prompt:

scsim <work library>.<VHDL configuration name> 

Refer to the VSS User's Guide for more details on VHDL simulation.

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