See Also

None	Allows you to turn off the advanced simulation option.
Test Bench mode	Allows you to set the following options to specify and run a test bench after compilation of the design: Test Bench file Allows you to specify the test bench file, which can a Verilog Design File (.v), VHDL Design File (.vhd), Verilog Test Bench File (.vt), or VHDL Test Bench File (.vht). Verilog Test Bench Files and VHDL Test Bench Files are essentially Verilog Design Files and VHDL Design Files, respectively, with a different extensions to indicate that they are test bench files. Test Bench entity name Allows you to specify the name of the design entity in the test bench file. Test Bench design instance name Allows you to specify the design instance name in the corresponding VHDL Design File or VHDL Test Bench File. This option is not available for Verilog HDL designs. Run for Allows you to specify the duration of the test bench simulation.
Command/macro mode	Allows you to specify a Model Technology™ ModelSim® Macro File (.do), TCL Script File (.tcl), or batch file that contains ModelSim commands, TCL script commands, or command-line commands for performing a timing simulation.

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