A basic functional block used in Verilog HDL. The following are gate primitives that are supported in the Quartus^® II software:

and      not
buf      notif0
bufif0   notif1
bufif1   or
nand     xnor
nor      xor

Gate primitives are similar to the wire, and, nand, nor, not, or, xnor, and xor primitives in Block Design Files (.bdf). See "Section 7: Gate and Switch Level Modeling" in the IEEE Std 1364-1995 IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language manual for more information on gate primitives.

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