A logic option that specifies whether the signal should be available throughout the device on the global routing paths. Global signals can be both pin- and logic-driven. Clock, output enable, register control, and memory control signals can be global signals. Turning this option on for a pin or a single-output logic function signal is equivalent to feeding the signal through a GLOBAL buffer. Turning this option off for a particular signal will prevent any of the Auto Global options from using the signal as an automatic global signal.
This option is available for all Altera® devices supported by the Quartus® II software.
The following settings are available for Cyclone™, Stratix™, and Stratix™ GX devices only:
| Priority Level | Assignment Type/Location | Affected Path(s) |
|---|---|---|
| 1 |
Point-to-point assignment from source to destination (register or memory that is the intended global path). |
Includes the path defined by source and destination. |
| 2 | Single point assignment to any node. | Includes all fan-outs of the specified node. |
Entity Settings File (.esf) timing assignment for point-to-point assignments uses the following syntax:
<source name>-> <destination name>: GLOBAL_SIGNAL = (ON|OFF|"GLOBAL CLOCK"|"REGIONAL CLOCK"|"FAST REGIONAL CLOCK")
ESF timing assignment for single-point assignments uses the following syntax:
<name>: GLOBAL_SIGNAL = (ON|OFF|"GLOBAL CLOCK"|"REGIONAL CLOCK"|"FAST REGIONAL CLOCK")
For Stratix and Stratix GX devices only, a setting of ON is equivalent to "GLOBAL CLOCK".
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