A feature available in selected Mercury^™ devices that employs a phase-locked loop (PLL). The HSDI (High-Speed Differential Interface) PLL multiplies an incoming clock signal by a factor of (2-12), 14, 16, 18, or 20 and provides the newly created "fast" clock to HSDI transmitters and receivers. The HSDI PLL is a special high-speed PLL designed for use by the CDR circuitry

You can take advantage of the CDR receiver PLL and the CDR transmitter PLL with both the altcdr_rx and altcdr_tx megafunctions.

The HSDI PLL can also be used as an LVDS receiver or LVDS transmitter PLL. You can take advantage of the LVDS PLL with the altlvds_rx and altlvds_tx megafunctions.