Megafunction

divide (Divider) Megafunction

Parameterized divider megafunction. Altera® recommends using lpm_divide rather than divide for divider functions. The divide megafunction is provided only for backward compatibility.

Altera recommends instantiating this function as described in Using the MegaWizard® Plug-In Manager.

This topic contains the following information:

 

AHDL Function Prototype (port name and order also apply to Verilog HDL):

 
FUNCTION divide (numerator[WIDTH_N-1..0], denominator[WIDTH_D-1..0], clock)
   WITH (WIDTH_N, WIDTH_D, WIDTH_Q, WIDTH_R, WIDTH_D_MIN,
      LPM_PIPELINE, PIPELINE_DELAY)
   RETURNS (quotient[WIDTH_Q-1..0], remainder[WIDTH_R-1..0];

 

VHDL Component Declaration:

 
COMPONENT divide
   GENERIC ( WIDTH_Q: POSITIVE;
             WIDTH_N: POSITIVE;
             WIDTH_D: POSITIVE;
             WIDTH_R: POSITIVE;
             LPM_NREPRESENTATION: STRING := "UNSIGNED"
             LPM_DREPRESENTATION: STRING := "UNSIGNED"
             LPM_PIPELINE: INTEGER := 0;
             LPM_TYPE: STRING := "LPM_DIVIDE";
             LPM_HINT: STRING := "UNUSED");
			 
   PORT    ( numerator: IN STD_LOGIC_VECTOR(WIDTH_N-1 DOWNTO 0);
             denominator: IN STD_LOGIC_VECTOR(WIDTH_D-1 DOWNTO 0);
             aclr, clock: IN STD_LOGIC := '0'
             clken: IN STD_LOGIC := '1';
             quotient: OUT STD_LOGIC_VECTOR(WIDTH_N-1 DOWNTO 0);
             remainder: OUT STD_LOGIC_VECTOR(WIDTH_D-1 DOWNTO 0));
END COMPONENT;

 

VHDL LIBRARY-USE Declaration

 
LIBRARY lpm;
USE lpm.lpm_components.all;

 

Port Descriptions:

INPUT PORTS

Port Name Description
numerator[] Input port WIDTH_N wide.
denominator[] Input port WIDTH_D wide. If the denominator[] value is known to be always greater than or equal to a fixed value, you can specify the optional WIDTH_D_MIN parameter to help minimize the design size.
clock Clock input. You must connect the clock input if you set LPM_PIPELINE to > 1.

OUTPUT PORTS

Port Name Description
quotient[] Output port WIDTH_Q wide.
remainder[] Output port WIDTH_R wide.

 

Parameter Descriptions:
Parameter Type Required Description
WIDTH_N Integer Yes Width of the numerator[] port.
WIDTH_D Integer Yes Width of the denominator[] port.
WIDTH_Q Integer Yes Width of the quotient[] port, usually equal to WIDTH_N. If WIDTH_D_MIN is used, this value must be specified as WIDTH_N - WIDTH_D_MIN + 1.
WIDTH_R Integer Yes Width of the remainder[] port, which must be specified as MIN(WIDTH_N, WIDTH_D).
WIDTH_D_MIN Integer No Minimum width of the denominator port, if known. 1 <= WIDTH_D_MIN <= MIN(WIDTH_N, WIDTH_D). Example: If the denominator port is known to be always greater than or equal to H"10", WIDTH_D_MIN can be set to 5. The default value is 1.
LPM_PIPELINE Integer No Specifies the number of Clock cycles of latency associated with the quotient[] and remainder[] outputs. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. If omitted, the default is 0 (non-pipelined). You cannot specify a value for the LPM_PIPELINE parameter that is higher than WIDTH_Q.
PIPELINE_DELAY Integer No Shifts the placement of the pipeline registered stages. By default, WIDTH_Q / 2 starts at the middle stage. Specify 0 to start at the last stage. Specify WIDTH_Q - 1 to start at the first stage. The default value is WIDTH_Q / 2.  Example

You can pipeline a design by connecting the clock input and specifying the number of clock cycles of latency with the LPM_PIPELINE parameter. You may also be able to increase the performance by controlling the placement of the pipeline registered stages with the PIPELINE_DELAY parameter.

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