ECUT_CUT_PLL_CLKIN_TOO

Input frequency of <number> for ClockLock PLL <name> is greater than maximum operational frequency of <number> for <name> I/O standard or internal clock network assigned to clock input pin <name>

CAUSE:

You specified an input frequency for the specified ClockLock PLL that is greater than the specified maximum operational frequency permitted for the specified clock input pin driving the ClockLock PLL. The speed grade of the target device you specified for the current design limits the maximum operational frequency. The internal clock network of the clock input pin may also limit the maximum operational frequency. Or, if you assigned an I/O standard to the clock input pin, the I/O standard you assigned may also limit the maximum operational frequency.

ACTION:

If possible, select another device with a faster speed grade. Otherwise, reduce the output frequency for the ClockLock PLL.

- PLDWorld -

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