ECUT_CUT_PLL_FBIN_TOO

Input clock frequency of <number> for ClockLock PLL <name> is greater than maximum operational frequency for <name> I/O standard or internal clock network assigned to <number> for external feedback input pin <name>

CAUSE:

You specified an input clock frequency for the specified ClockLock PLL that is greater than the specified maximum operational frequency permitted for the specified external feedback input pin driving the ClockLock PLL. The speed grade of the target device you specified for the current design limits the maximum operational frequency. The internal clock network of the external feedback input pin may also limit the maximum operational frequency. Or, if you assigned an I/O standard to the external feedback input pin, the I/O standard you assigned may also limit the maximum operational frequency.

ACTION:

If possible, select another device with a faster speed grade. Otherwise, reduce the input clock frequency for the ClockLock PLL.

- PLDWorld -

Created by chm2web html help conversion utility.