| CAUSE: | The ClockLock PLL specified in the top-level message has an output frequency that is greater than the specified maximum operational frequency for the specified destination and specified I/O standard. The speed grade of the target device you specified for the current design limits the maximum operational frequency. The internal clock network of the destination may also limit the maximum operational frequency. Or, if the destination is an I/O pin, the I/O standard you assigned to that pin may also limit its maximum operational frequency. |
| ACTION: | If possible, select another device with a faster speed grade. Otherwise, reduce the output frequency for the ClockLock PLL. |
See also:
Overview: Making Assignments
Overview: Using the MegaWizard Plug-In Manager
Specifying the Device Family & Device for Compilation
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