| CAUSE: | The Fitter cannot place the ClockLock PLL in the device due to device constraints, the global clk0 pin feeds both a register and the PLL through the clock0 port, or the global clk1 signal feeds a register and the PLL. |
| ACTION: | Reduce the number of ClockLock PLLs in the project, make sure the global clk0 pin does not conflict with the clock0 port of the PLL, and that the global clk1 pin does not feed another register as well as the PLL. |
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |