Quartus

clock0 and clock1 input ports of LVDS transmitter <name> must be fed by the same LVDS transmitter PLL

CAUSE: You did not feed the clock0 and clock1 input ports of the specified LVDS transmitter with the same LVDS transmitter PLL.
ACTION: Edit the design so that one LVDS transmitter PLL feeds the LVDS transmitter.

- PLDWorld -

 
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