Quartus

Neither clock0 port nor clock1 port of <ClockLock PLL> <name> feeds an output pin, but ClockLock PLL is using the fbin port

CAUSE: The specified ClockLock PLL uses the fbin port, but neither its clock0 port nor its clock1 port feeds an output pin. Either the clock0 or clock1 port must feed an output pin.
ACTION: Edit the design so that either the clock0 or clock1 port feeds an output pin.

- PLDWorld -

 
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