Quartus

ClockLock PLLs <name> and <name>, both fed by input clock pin <name>, require <number> global clock lines but current device only allows <number>

CAUSE: In the design, the specified input clock pin feeds both of the specified ClockLock PLLs. This requires the two ClockLock PLLs to be placed next to each other and to access the specified number of global clock lines. However, the current device allows adjacent ClockLock PLLs to access only the specified number of global clock lines.
ACTION: Modify the design so that the specified input clock pin does not feed both ClockLock PLLs, or change the device.

See also:

Assigning Pins
Changing Assignments
Deleting Assignments in the Assignment Organizer
Overview: Making Assignments
Overview: Working with Assignments in the Floorplan Editor
Specifying the Device Family & Device for Compilation

- PLDWorld -

 
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