| CAUSE: | The clock0 port of the specified LVDS receiver PLL feeds logic that is not a clk0 port of an LVDS receiver. The clock0 port of the LVDS receiver PLL must feed only the clk0 port of an LVDS receiver. |
| ACTION: | Edit the design so that the clock0 port of the LVDS receiver PLL feeds only the clk0 port of an LVDS receiver. |
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