Quartus

Port of type <clock0> of <LVDS transmitter PLL> <name> must feed only clk0 port of LVDS transmitter

CAUSE: The specified clock0 port of the specified LVDS transmitter PLL feeds logic that is not the clk0 port of an LVDS transmitter. The clock0 port of the LVDS transmitter PLL can feed only the clk0 port of an LVDS transmitter.
ACTION: Edit the design so the clock0 port of the LVDS transmitter PLL feeds only the clk0 port of an LVDS transmitter.

- PLDWorld -

 
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