CAUSE: | The specified clock1 port of the specified LVDS transmitter PLL feeds logic that is not a clk1 port of an LVDS transmitter and/or feeds too many output pins. The clock1 port of the LVDS transmitter PLL can feed only the clk1 port of an LVDS transmitter and no more than one output pin. |
ACTION: | Edit the design so the clock1 port of the LVDS transmitter PLL feeds only the clk1 port of an LVDS transmitter and no more than one output pin. |
- PLDWorld - |
|
Created by chm2web html help conversion utility. |