Quartus

Port of type <type> of LVDS transmitter PLL <name> can fan out only to clk1 port of LVDS transmitter cell and/or core logic through global clock lines

CAUSE: The clk2 port of the specified LVDS transmitter PLL feeds logic that is not a clk1 port of an LVDS transmitter and/or does not feed core logic through global clock lines. The clk2 port of the specified LVDS transmitter PLL can feed only the clk1 port of an LVDS transmitter and/or to core logic through global clock lines.
ACTION: Edit the design so the clk2 port of the LVDS transmitter PLL feeds only the clk1 port of an LVDS transmitter and/or to core logic through global clock lines.

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