Quartus

Clock0 input of LVDS receiver <name> must be fed by LVDS receiver PLL clock0

CAUSE: The clock0 input port of the specified LVDS receiver is not fed by the LVDS receiver PLL clock0, but it must be fed by the LVDS receiver PLL clock0.
ACTION: Connect the clock0 to the LVDS receiver PLL clock0.

- PLDWorld -

 
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