| CAUSE: | You connected the ClockLock feedback in port of the specified ClockLock PLL, but the ClockLock PLL is not in external feedback mode. When the ClockLock PLL is not in external feedback mode, it cannot use the ClockLock feedback in port. |
| ACTION: | Modify the design to change the mode of the ClockLock PLL to external feedback or to disconnect the ClockLock feedback in port. |
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- PLDWorld - |
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