| CAUSE: | You assigned the specified ClockLock PLL to the specified PLL location. However, the PLL uses the locked output port but the PLL location on the device does not have one. |
| ACTION: | Modify the design so that the specified PLL does not use a locked output port, or assign the PLL to a PLL location that has a locked output port. |
See also:
Assigning an Entity or Node to a Location
Changing Assignments
Deleting Assignments in Assignment Organizer
Overview: Making Assignments
Overview: Working with Assignments in the Floorplan Editor
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