Quartus

cruclk input frequency <name> of GXB receiver channel <name> does not equal output clock frequency <name> of source PLL

CAUSE: The specified cruclk input frequency of the specified gigabit transceiver block (GXB) receiver channel does not match the specified output clock frequency of the PLL that feeds this connection. The cruclk input frequency of the GXB receiver channel must match the output clock frequency of the source PLL.
ACTION: Modify the design so that the cruclk input frequency of the GXB receiver channel matches the output clock frequency of the source PLL.

- PLDWorld -

 
Created by chm2web html help conversion utility.