Quartus

Fast PLL <name> does not use the comparator input port, but the enable0 and enable1 outputs must come from the same counter

CAUSE: The specified fast PLL does not use comparator input and the enable0 and enable1 outputs come from different counters. If the comparator input port is not used, the enable0 and enable1 outputs must come from the same counter.
ACTION: Modify the design so that enable0 and enable1 outputs come from the same counter of the fast PLL.

- PLDWorld -

 
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