| CAUSE: | You assigned the specified fast PLL or enhanced PLL to the specified location. However, the Fitter cannot place the PLL because the specified output clock port of the PLL needs more regional or global clocks than the PLL location on the device can provide. |
| ACTION: | Modify the design so that the specified PLL uses fewer output clock ports, or assign the PLL to a PLL location that has enough regional or global clocks for the output clock port. |
See also:
Assigning an Entity or Node to a Location
Changing Assignments
Deleting Assignments in the Assignment Organizer
Overview: Making Assignments
Overview: Working with Assignments in the Floorplan Editor
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