| CAUSE: | You selected a target device for the current project. The Fitter cannot place the specified fast PLL or enhanced PLL in the PLL location because the PLL has an input clock that is not an I/O cell. |
| ACTION: | Modify the design so that the specified PLL uses an I/O cell as an input clock, or assign the PLL to a fast or enhanced PLL location that accepts a non-I/O cell input clock. |
See also:
Assigning an Entity or Node to a Location
Overview: Making Assignments
Overview: Working with Assignments in the Floorplan Editor
Specifying the Device Family & Device for Compilation
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- PLDWorld - |
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