CAUSE: | You assigned the specified fast PLL or enhanced PLL to the specified location. However, the Fitter cannot place the PLL because the PLL requires more clock output ports than are available in the PLL location. |
ACTION: | Modify the design so that the specified PLL uses fewer clock output ports, or assign the PLL to a PLL location which has enough clock output ports. |
See also:
Assigning an Entity or Node to a Location
Changing Assignments
Deleting Assignments in the Assignment Organizer
Overview: Making Assignments
Overview: Working with Assignments in the Floorplan Editor
- PLDWorld - |
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