| CAUSE: | The clock input port of the specified receiver fast PLL is not driven by an I/O pin. However, for better receiver input skew margin (RSKM) performance a receiver fast PLL requires a dedicated connection between an I/O pin and the clock input port. |
| ACTION: | Modify the design so that an I/O pin drives the receiver fast PLL. |
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |