Quartus

Clock input pin <name> drives fast PLL <name>, but also drives other logic -- must drive only fast PLL

CAUSE: The specified clock input pin drives the specified receiver fast PLL but also drives other logic. However, for better receiver input skew margin (RSKM) performance, a receiver fast PLL requires a dedicated connection between the clock input pin and the PLL.
ACTION: Modify the design so that the clock input pin drives only the receiver fast PLL.

- PLDWorld -

 
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