| CAUSE: | You used the Create HDL Design File for Current File command (Tools menu) to create a Verilog Design File (.v) or VHDL Design File (.vhd) from the current design file. However, the current design name contains an illegal character for Verilog HDL, "/" or "-", or contains a Verilog HDL keyword. This can cause the Verilog Design File (.v) to not compile once it is generated. |
| ACTION: | Rename the design to exclude illegal name characters or Verilog HDL keywords and create the HDL design file again. |
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |