| CAUSE: | You used the Create HDL Design File for Current File command (Tools menu) to create a Verilog Design File (.v) or VHDL Design File (.vhd) from the current design file. However, the current design name contains an illegal character for Verilog HDL, "/", "_", or "-", or contains a VHDL keyword. This can cause the VHDL Design File (.vhd) to not compile once it is generated. |
| ACTION: | Rename the design to exclude illegal name characters or VHDL keywords and create the HDL design file again. |
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