| CAUSE: | You used the Create HDL Design File for Current File command (Tools menu) to create a VHDL Design File (.vhd) or a Verilog Design File (.v) for the current Block Design File (.bdf) or Graphic Design File (.gdf), but the specified flipflop primitive is missing one or more necessary input, output, or clock signals. The Quartus II software cannot convert a flipflop primitive without properly connected input, output, or clock signals into a valid group of VHDL or Verilog statements. |
| ACTION: | Make sure the necessary data input, output, and clock signals are connected to the flipflop primitive and create the HDL design file again. |
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