| CAUSE: | You used the Create HDL Design File for Current File command (Tools menu) to create a VHDL Design File (.vhd) or a Verilog Design File (.v) for the current Block Design File (.bdf) or Graphic Design File (.gdf), but the specified LATCH primitive is missing input, enable, or output signals. The Quartus II software cannot convert a LATCH primitive without properly connected input, enable, or output signals into a valid group of VHDL or Verilog statements. |
| ACTION: | Make sure the necessary input, enable, and output signals are connected to the LATCH primitive and create the HDL design file again. |
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- PLDWorld - |
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