| CAUSE: | You used the Create HDL Design File for Current File command (Tools menu) to create a VHDL Design File (.vhd) or a Verilog Design File (.v) for the current Block Design File (.bdf) or Graphic Design File (.gdf), but the specified TRI primitive is missing one or more input, output enable, or output signals. The Quartus II software cannot convert a TRI primitive without properly connected input, output enable, or output signals into a valid group of VHDL or Verilog statements. |
| ACTION: | Make sure the necessary input, output enable, and output signals are connected to the TRI primitive and create the HDL design file again. |
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |