| CAUSE: | In a Verilog HDL or VHDL design file, you created a shift operator with the specified variable shift distance, which you specify using a register. However, the shift distance is greater than the specified width of the data that you are shifting. For example, this error can occur if you shift an 8-bit register by the value of a register with 4 or more bits, where the shift distance can be up to 16 bits. This limitation will be removed in a future version of the Quartus II software. |
| ACTION: | Change the size of the shift distance register so the shift distance can never be greater than the data width. |
See also:
Section 4.1.12 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
Section 7.2.3 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual
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