| CAUSE 1: | You specified the target device and compiled the current design, but the design requires too many logic cells to fit in the selected device. |
| ACTION: | Reduce the number of logic cells or select a larger device. You can try to reduce the number of logic cells in APEX and Stratix devices by turning on Perform WYSIWYG primitive resynthesis in the Netlist Optimizations page of the Settings dialog box and setting the Optimization Technique logic option to Area. |
| CAUSE 2: | You directed the Compiler to select the target device, specified the characteristics for the devices, and compiled the current design. However, the design requires too many logic cells to fit in any device. |
| ACTION: | Reduce the number of logic cells, change which devices appear in the Available devices list of the Devices page of the Settings dialog box, or select another device family. You can try to reduce the number of logic cells in APEX and Stratix devices by turning on Perform WYSIWYG primitive resynthesis in the Netlist Optimizations page of the Settings dialog box and setting the Optimization Technique logic option to Area. |
See also:
Optimizing Netlists During Synthesis & Fitting
Overview: Making Assignments
Specifying the Device Family & Device for Compilation
Specifying Settings for Default Logic Options
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