| CAUSE 1: | You specified a target device for the current design, but the design contains too many ClockLock PLLs to fit in the target device. |
| ACTION: | Reduce the number of Clocklock PLLs in the design or select a larger device. |
| CAUSE 2: | You directed the Compiler to select a target device for the current design, and specified the devices from which you want the Compiler to select the target device. However, the design contains too many ClockLock PLLs to fit in any of the devices you specified. |
| ACTION: | Reduce the number of Clocklock PLLs in the design, specify different devices, or select another device family. |
See also:
Specifying the Device Family & Device for Compilation
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- PLDWorld - |
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