ESGN_EXPECTED_FILE_NOT

Can't continue processing -- expected file <name> is missing

CAUSE:

You performed one of the following actions:

Analyzed a file
Created an AHDL Include File (.inc)
Created a Block Symbol File (.bsf)
Created a VHDL Design File (.vhd) or Verilog Design File (.v) for the current Block Design File (.bdf).

However, the Quartus II software cannot continue the process because the specified file that is required for the process is missing.

ACTION:

Verify that the specified file exists. If the file exists, create the directory for the file or specify the correct path for the file and then restart the process.

- PLDWorld -

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