Quartus

Net <name> cannot be assigned more than one value


CAUSE: In the Continuous Assignments section of a Verilog Design File (.v), you assigned more than one value to the specified net. You can assign only one value to (that is, use only one Continuous Assignment Statement for) a net in a Verilog Design File.
ACTION: Make sure the Verilog Design File contains only one Continuous Assignment Statement that assigns a value to the signal.

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