| CAUSE: | In the Verilog Quartus Mapping File (.vqm) that you generated with another EDA tool, such as Synplicity Synplify software, the Defparam Statement is in the wrong position in a Module Instantiation. The Defparam Statement must immediately follow the name of the instantiated module to which it assigns a parameter value. This error may also have occurred if you created or edited a VQM File manually. |
| ACTION: | Change the position of the Defparam Statement. In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact Altera Applications or the EDA tool vendor support for more information. |
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