In a Module Instantation port connection in the Verilog Quartus Mapping File (.vqm) that you generated with another EDA tool, such as Synplicity Synplify software, you used the logical negation operator (!) with the specified output port or specified bit-select or part-select of a declared vector net. However, you cannot use a logical negation operator with these type of ports. This error may also have occurred if you created or edited a VQM File manually.

Replace the port connection containing the logical negation operator with a temporary wire net. For example, for the illegal Module Instantiation

example example1(in, !out)

where out is an output port, create a temporary net called temp:

wire temp;
assign temp = !out

Then change the Module Instantiation to example example1(in, temp).

In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact Altera Applications or the EDA tool vendor support for more information.