| CAUSE: | In a Module Instantation port connection in the Verilog Quartus Mapping File (.vqm) that you generated with another EDA tool, such as Synplicity Synplify software, you connected the specified scalar port in a WYSIWYG primitive to a vector signal. You cannot connect a port with one bit to a signal with more than one bit. This error may also have occurred if you created or edited a VQM File manually. |
| ACTION: | Make sure the port with one bit in the WYSIWYG primitive connects only to a signal with one bit. In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact Altera Applications or the EDA tool vendor support for more information. |
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