Quartus

Verilog HDL error at <location>: variable index to array <name> is not within range

CAUSE: In a Verilog Design File (.v) at the specified location, you used a variable index to the specified array, but the variable index is not within the boundaries of the range specified for the variable.
ACTION: Increase the array size to include the whole variable value range.

See also:

Sections 3.2, 3.10, and 7.1 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

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