Quartus

Verilog HDL Macro Definition syntax error at <location>: illegal character in macro parameter near <name>

CAUSE: In a Macro Definition at the specified location in a Verilog Design File (.v), you specified parameters for a macro, but the macro parameter contains illegal characters.
ACTION: Make sure you use legal characters and correct syntax for variables, numbers, and other text in the macro parameters.

See also:

Section 19.3 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual

- PLDWorld -

 
Created by chm2web html help conversion utility.