| CAUSE: | In a Verilog Design File (.v) at the specified location, you used what appears to be a Compiler Directive (such as `define); however, the Compiler Directive keyword you used is not recognized by Integrated Synthesis. |
| ACTION: | Edit the design to use the correct Compiler Directive keyword. |
See also:
Section 19 of the IEEE Std. 1364-2001 IEEE Standard Verilog Hardware Description Language manual
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